Extends from Modelica.Icons.Package (Icon for standard packages).
Name | Description |
---|---|
DLATRAM | Level sensitive Random Access Memory |
DLATROM | Level sensitive Read Only Memory |
Level sensitive Random Access Memory
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active read enable RE:
RE | Addr | DataOut |
0 | * | Z over all |
1 | no X in Addr | DataOut=m(Addr) |
1 | X in Addr | X over all |
X | * | X over all |
Truth Table for high active write enable WE:
WE | Addr | Memory |
0 | * | no write |
1 | no X in Addr | m(Addr)=DataIn |
1 | X in Addr | no write |
X | no X in Addr | m(Addr)=X over all |
X | X in Addr | no write |
* = do not care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U' Z = L.'Z'
Simultaneous read/write operations are allowed. Firstly Write is carried out, then Read.
Name | Description |
---|---|
tHL | High->Low delay [s] |
tLH | Low->High delay [s] |
strength | output strength |
n_addr | addr width |
n_data | data width |
table data definition | |
fileName |
Name | Description |
---|---|
RE | read enable |
WE | write enable |
addr[n_addr] | address |
dataIn[n_data] | data input |
dataOut[n_data] | data output |
Level sensitive Read Only Memory
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active read enable RE:
RE | Addr | DataOut |
0 | * | Z over all |
1 | no X in Addr | DataOut=m(Addr) |
1 | X in Addr | X over all |
X | * | X over all |
* = do not care 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U' Z = L.'Z'
Name | Description |
---|---|
tHL | High->Low delay [s] |
tLH | Low->High delay [s] |
strength | output strength |
n_addr | addr width |
n_data | data width |
table data definition | |
fileName | File where matrix for memory is stored |
Name | Description |
---|---|
RE | read enable |
addr[n_addr] | address |
dataOut[n_data] | data output |