Modelica.Electrical.Digital.Memories

Information

Extends from Modelica.Icons.Package (Icon for standard packages).

Package Content

Name Description
Modelica.Electrical.Digital.Memories.DLATRAM DLATRAM Level sensitive Random Access Memory
Modelica.Electrical.Digital.Memories.DLATROM DLATROM Level sensitive Read Only Memory

Modelica.Electrical.Digital.Memories.DLATRAM Modelica.Electrical.Digital.Memories.DLATRAM

Level sensitive Random Access Memory

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active read enable RE:

RE Addr DataOut
0 * Z over all
1 no X in Addr DataOut=m(Addr)
1 X in Addr X over all
X * X over all

Truth Table for high active write enable WE:

WE Addr Memory
0 * no write
1 no X in Addr m(Addr)=DataIn
1 X in Addr no write
X no X in Addr m(Addr)=X over all
X X in Addr no write

  *  = do not care
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U'
  Z  = L.'Z'

Simultaneous read/write operations are allowed. Firstly Write is carried out, then Read.

Parameters

NameDescription
tHLHigh->Low delay [s]
tLHLow->High delay [s]
strengthoutput strength
n_addraddr width
n_datadata width
table data definition
fileName 

Connectors

NameDescription
REread enable
WEwrite enable
addr[n_addr]address
dataIn[n_data]data input
dataOut[n_data]data output

Modelica.Electrical.Digital.Memories.DLATROM Modelica.Electrical.Digital.Memories.DLATROM

Level sensitive Read Only Memory

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active read enable RE:

RE Addr DataOut
0 * Z over all
1 no X in Addr DataOut=m(Addr)
1 X in Addr X over all
X * X over all

  *  = do not care
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U'
  Z  = L.'Z'

Parameters

NameDescription
tHLHigh->Low delay [s]
tLHLow->High delay [s]
strengthoutput strength
n_addraddr width
n_datadata width
table data definition
fileNameFile where matrix for memory is stored

Connectors

NameDescription
REread enable
addr[n_addr]address
dataOut[n_data]data output
Automatically generated Tue Apr 05 09:36:18 2016.